FIG. 1 shows a signal reproduction circuit studied as a premise of the present invention. The signal reproduction circuit CDR C shown in FIG. 1 is a structure example similar to that of Patent Document 1. The signal reproduction circuit CDR_C is configured with: a data judgment/phase comparison circuit DD/PD; an averaging circuit AV; a phase pointer control circuit PCON; a phase interpolation circuit PI; and an N-phase clock generation circuit NPG.
The data judgment/phase comparison circuit DD/PD judges a data input Din in synchronization with a clock phase for data acquisition among n-phase clocks CLKn, and outputs the judgment result to a data output Dout. Simultaneously, the data judgment/phase comparison circuit DD/PD compares phases of the data input Din with the n-phase clocks CLKn with using a plurality of clock phases of the n-phase clocks CLKn, and outputs an Early signal when the phase of the n-phase clock CLKn is earlier than that of the data input Din and a Late signal when the phase of the n-phase clock CLKn is later than that of the data input Din.
The averaging circuit AV calculates an average shift in phase between the n-phase clock CLKn and the data input Din from a result of the phase comparison outputted from the data judgment/phase comparison circuit DD/PD, that is, from calculation of Early and Late signals for a certain period. As a result, when the phases of the n-phase clocks CLKn are later than the phase of the data input Din on average, an Up signal is outputted, and, when the phases of the n-phase clocks CLKn are earlier than the phase of the data input Din on average, a Down signal is outputted. A processing by the averaging circuit AV is substantially equivalent to a processing of using a low-pass filter, and an analog low-pass filter may be used in place of the averaging circuit AV.
The phase pointer control circuit PCON outputs a phase control signal Sph for controlling an output phase of the phase interpolation circuit PI based on the above-described Up signal and the Down signal. When the averaging circuit AV outputs the Up signal, it controls so that a phase of an output clock of the phase interpolation circuit is advanced. Conversely, when the averaging circuit AV outputs the Down signal, it controls so that the phase of the output clock of the phase interpolation circuit is delayed.
The phase interpolation circuit PI is typically operated by changing a phase of a reference clock CLKref inputted from an outside based on the phase control signal Sph. However, an essential function of the phase interpolation circuit PI is to change a phase of a clock CLK outputted based on the phase control signal Sph. For example, a method without using the reference clock can be also considered such that a source oscillator capable of changing the output phase based on the phase control signal Sph is embedded in the phase interpolation circuit PI.
The N-phase clock generation circuit NPG is a circuit for generating n-phase clocks from the single-phase clock CLK outputted by the phase interpolation circuit PI, which is required at the data judgment/phase comparison circuit DD/PD. At this time, a specific clock phase among the n-phase clocks is outputted to an outside of the signal reproduction circuit CDR_C as a reproduction clock CLKout.
According to the signal reproduction circuit CDR_C of FIG. 1, a clock for data acquisition among the n-phase clocks CLKn always follows the phase of the data input Din, so that a correct data judgment can be achieved.
Each of FIGS. 2A and 2B shows a structure example of the data judgment/phase comparison circuit DD/PD studied as a premise of the present invention. However, these figures show only an essential part of the entire circuit, and a retiming circuit among signals and others are omitted.
FIG. 2A shows a structure of a data judgment/phase comparison circuit DD/PD of an Alexander's method disclosed in Non-Patent Document 1. To the data judgment/phase comparison circuit DD/PD shown in FIG. 2A, a data input Din and two-phase clocks clkD and clkE which are shifted from each other by a half one symbol period are inputted, and the circuit outputs a data output Dout and phase comparison signals Early and Late. At this time, a result obtained from the two-phase clocks by judging the data input Din in synchronization with the clkD is outputted as the Dout.
FIG. 2B shows a structure of a data judgment/phase comparison circuit DD/PD of an eye tracking method disclosed in Patent Document 1. To the data judgment/phase comparison circuit DD/PD shown in FIG. 2B, the data input Din and three-phase clocks clkD, clkE, and clkL shifted from each other by a quarter time the one symbol period are inputted, and the circuit outputs a data output Dout and phase comparison signals Early and Late. At this time, a result obtained from the three-phase clocks by judging the data input Din in synchronization with the clkD is outputted as the Dout.